1. Field of the Invention
The present invention generally relates to a static-type semiconductor memory device and a field effect transistor and methods of manufacturing the same, and, more particularly, to a thin film transistor (TFT), a method of manufacturing a TFT, a static-type semiconductor memory device provided with a memory cell having a complementary field effect transistor and a method of manufacturing the same. The present invention is particularly useful in conjunction with a CMOS-type SRAM (Static Random Access Memory) to which a TFT is applied.
2. Description of the Background Art
What is called a SRAM is already well known as a static-type semiconductor memory device. Since the present invention has the most preferable effects when it is applied to a SRAM, a SRAM will be described in the following.
FIG. 16A is an equivalent circuit diagram illustrating one memory cell in a conventional CMOS-type SRAM. FIG. 16B is a plan view schematically illustrating an arrangement in the memory cell in the SRAM illustrated in FIG. 16A. FIG. 16C is a cross sectional view schematically illustrating a cross sectional structure of the memory cell in the SRAM illustrated in FIG. 16A.
Referring to FIGS. 16A-16C, a flip-flop type memory cell is implemented, including two driver transistors (n-channel MOS transistors) Q3, Q4 having the gate electrodes and drain electrodes cross-coupled and two load transistors (p-channel MOS transistors) Q5, Q6 connected, respectively, to the drain electrodes of driver transistors. Two access transistors (n-channel MOS transistors) Q1, Q2 are connected, respectively, to the drain electrodes of the two driver transistors Q3, Q4. The gate electrodes of access transistors Q1, Q2 are connected to a word line WL. When the word line WL is selected, data held in driver transistors Q3, Q4 are transferred through access transistors Q1, Q2 to bit lines BLa, BLb. One memory cell node N1 is connected to the drain electrode of driver transistor Q3, to the gate electrode of driver transistor Q4, to the drain electrode of load transistor Q5, and to the gate electrode of load transistor Q6. The other memory cell node N2 is connected to the gate electrode of driver transistor Q3, to the drain electrode of driver transistor Q4, to the gate electrode of load transistor Q5, and to the drain electrode of load transistor Q6. Source electrodes of driver transistors Q3, Q4 are connected to a ground potential GND. Source electrodes of load transistors Q5 Q6 are connected to a supply potential Vcc.
The drain electrodes and the gate electrodes of driver transistors Q3, Q4 are mutually cross-connected to form a flipflop circuit having two stable states. This enables storing of bit data. Specifically, data of one bit can be stored by holding a state in which the potential of one memory cell node N1 is at "High" level, and the potential of the other memory cell node N2 is at "Low" level, or a state which is reverse to that state. When a desired memory cell is selected, i.e. when the word line WL is at "High" level, access transistors Q1, Q2 are brought to ON state. This causes memory cell nodes N1, N2 to be conduct to bit lines Bla, Blb. At this time, voltages corresponding to the states of respective driver transistors Q3, Q4 come to appear on bit lines BLa, BLb through access transistors Q1, Q2. Thus, data held in the memory cell is read. When data is written into the memory cell, voltages corresponding to desired states to be written are applied to respective bit lines BLa, BLb with access transistors Q1, Q2 in ON state. In order to maintain the state of storing data latched by the flip-flop circuit implemented with driver transistors Q3, Q4, current is supplied from supply potential Vcc through load transistors Q5, Q6.
As described above, a memory cell in a CMOS-type SRAM is implemented with six transistors Q1-Q6. Therefore, as illustrated in FIG. 16B, a region where four n-channel MOS transistors are formed and a region where two p-channel MOS transistors are formed are necessary for constituting a memory cell. In addition, as illustrated in FIG. 16C, a p-type well region (p-Well) and an n-type well region (n-Well) are necessary for forming the n-channel MOS transistors and the p-channel MOS transistors in a semiconductor substrate. Therefore, a large flat area is necessary for forming a memory cell in a CMOS-type SRAM as long as a bulk-type MOS transistor (a MOS transistor formed on the surface of a semiconductor substrate) is used. Accordingly, a memory cell in a CMOS-type SRAM implemented with a bulk MOS transistor is disadvantageous for achieving high density.
High resistance load type memory cell has one structure of a memory cell in SRAM for solving the above problem and enabling high densification. FIG. 17A is an equivalent circuit diagram illustrating a structure of a memory cell in a SRAM of a high resistance load type. FIG. 17B is a plan view schematically illustrating an arrangement in the memory cell illustrated in FIG. 17 A. FIG. 17C is a cross sectional view schematically illustrating a cross sectional structure of the memory cell illustrated in FIG. 17A.
Referring to FIGS. 17A-17C, a flip-flop type memory cell is implemented, including two driver transistors (n-channel MOS transistors) Q3, Q4 having the gate electrodes and drain electrodes respectively cross-coupled and two high resistance loads HR1, HR2 connected, respectively, to the drain electrodes of the driver transistors. Two access transistors (n-channel MOS transistors) Q1, Q2 are connected to the drain electrodes of two driver transistors Q3, Q4, respectively. The gate electrodes of access transistors Q1, Q2 are connected to a word line WL. When the word line WL is selected, data held in driver transistors Q3, Q4 are transferred through access transistors Q1, Q2 to bit lines BLa, BLb. One memory cell node N1 is connected to the drain electrode of driver transistor Q3 and to the gate electrode of driver transistor Q4. The other memory cell node N2 is connected to the gate electrode of drive transistor Q3 and to the drain electrode of driver transistor Q4. Source electrodes of driver transistors Q3, Q4 are connected to a ground potential GND. The drain electrodes of driver transistors Q3, Q4 are connected through high resistance loads HR1, HR2 to a supply potential Vcc.
In the high resistance load-type memory cell implemented as described above, driver transistors Q3, Q4 have the drain electrodes and gate electrodes mutually cross-connected to form a flip-flop circuit having two stable states as in a CMOS-type memory cell. This enables storing of bit data. The data reading operation and data writing operation are the same as in the above-described memory cell of CMOS type. This memory cell differs from the memory cell of CMOS type in that current is supplied from supply potential Vcc through high resistance loads HR1, HR2 for maintaining the state of storing data latched by the flip-flop circuit implemented with driver transistors Q3, Q4.
As described above, a high resistance load type memory cell is implemented with four transistors Q1-Q4 and two high resistance loads HR1, HR2. As illustrated in FIG. 17B, in order to form a high resistance load type memory cell, first, a region where four n-channel MOS transistors are to be formed is secured. A high resistance load HR is formed on two n-channel MOS transistors constituting driver transistors Q3, Q4. As illustrated in FIG. 17C, only a p-type well region (p-Well) is necessary for implementing a high resistance load type memory cell. Therefore, the flat area necessary for a memory cell is smaller as compared to a memory cell of CMOS type which requires a p-type well and an n-type well in a memory cell. Accordingly, a high resistance load type memory cell is advantageous for high densification SRAM.
However, in the high resistance load type memory cell, current is supplied from supply potential Vcc through high resistance loads HR1, HR2 for maintaining state of storing data latched by the flip-flop circuit implemented with driver transistors Q3, Q4. It is desired that the current is small for suppressing power consumption during waiting. Therefore, it is necessary make the electrical resistance value of the high resistance loads as high as possible. However, there is a limit to the resistance of the resistance loads, and it is necessary that current flowing in the high resistance loads for holding data is larger than the leakage current in the case where the transistor is off. On the other hand, in the memory cell of CMOS type, current is supplied from supply potential Vcc through load transistors (p-channel MOS transistors) Q5, Q6 for maintaining the state of storing data latched by the flip-flop circuit. Therefore, it is possible to reduce current consumption during waiting to the level of the junction leakage current. As described above, although the high resistance load type memory cell is advantageous for high densification of a SRAM, the memory cell of CMOS type is advantageous for reducing current consumption to hold the state of storing data, i.e. for suppressing power consumption during waiting.
In consideration of the above respects, a structure of a CMOS-type memory cell capable of achieving high densification of a SRAM is proposed. FIG. 18A is a plan view schematically illustrating an arrangement in a memory cell implemented by reducing the occupied flat area in the memory cell of CMOS type illustrated in FIG. 16A. FIG. 18B is a cross sectional view corresponding to FIG. 18A.
Referring to FIGS. 16A and 18A-18B, p-channel thin film transistors (TFTs) are adapted, as load transistors Q5, Q6, instead of bulk-type p-channel MOS transistors. Therefore, as illustrated in FIG. 18A, a region for formation of four n-channel MOS transistors is required for implementing a memory cell. p-channel TFTs constituting load transistors Q5, Q6 are formed on n-channel MOS transistors constituting driver transistors Q3, Q4. As illustrated in FIG. 18B, four bulk-type n-channel MOS transistors are formed in a p-type well region (p-Well). If p-channel TFTs are adapted as load transistors like this, only a p-type well region is required for forming one memory cell. Therefore, it is possible to reduce the flat area occupied by a memory cell CMOS type and to provide a structure of a memory cell of CMOS type advantageous for high densification by adapting a p-channel TFT.
A memory cell in a SRAM of CMOS type in which a p-channel TFT including a polycrystalline silicon layer is adapted as a load transistor is disclosed in "A 25 .mu.m.sup.2 New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity" IEDM, 1988, pp. 48-51. FIG. 19 is a partial plan view illustrating an arrangement in only the upper layer part in such a memory cell in a SRAM. FIG. 20 is a partial cross sectional view illustrating a cross sectional structure taken along line XX--XX in FIG. 19. FIGS. 21A-21C are partial cross sectional views illustrating a method of manufacturing the memory cell illustrated in FIG. 20, particularly, sequentially illustrating cross sectional structures in respective steps of a method of forming a p-channel TFT constituting a load transistor.
Referring to FIGS. 19 and 20, an n-type well region 502 and a p-type well region 503 are sequentially formed on a p-type silicon substrate 501. An n.sup.+ impurity region 209 of an n-channel MOS transistor constituting a driver transistor or an access transistor is formed in p-type well region 503. An isolating oxide film 200 is formed for isolating each n-channel MOS transistor. Gate electrodes 201, 202 of a first polycrystalline silicon layer are formed on p-type well region 503 with a gate insulating film 210 interposed therebetween. Gate electrodes 201, 202 constitute the gate of an access transistor or a driver transistor. A gate electrode 204 of a second polycrystalline silicon layer is formed on gate electrodes 201, 202 with an insulating film interposed therebetween. Gate electrode 204 constitutes the gates of p-channel TFTs as load transistors Q5, Q6. A source region 206a, a channel region 206, and a drain region 206b of a TFT of a third polycrystalline silicon layer are formed on gate electrode 204 with a gate insulating film 212 interposed therebetween. Source region 206a of the TFT constitutes power supply interconnection line Vcc. Drain region 206b of each TFT is connected through a contact hole 205 to gate electrode 204 of another TFT. An interlayer insulating film 214 is formed to cover each transistor. A refractory metal layer 207a is formed to be in contact with n.sup.+ impurity region 209 through a contact hole 208. An interlayer insulating 216 is formed on refractory metal layer 207a. An aluminum metal layer 207b is connected to refractory metal layer 207a. A bit line is constituted with aluminum metal layer 207b.
A method of manufacturing the memory cell in a SRAM formed as described above, particularly a method of manufacturing a p-channel TFT, will be described with reference to FIGS. 21A-21C.
Referring to FIG. 21A, an isolating oxide film 200, an n.sup.+ impurity region 209, a gate insulating film 210 and gate electrodes 201, 202 are formed in a p-type well region 503 to constitute a driver transistor or an access transistor. An interlayer insulating film 211 is formed to cover each transistor. A second layer of a polycrystalline silicon layer is formed on interlayer insulating film 211 by a low pressure CVD process, for example. Arsenic ions are implanted into the polycrystalline silicon layer, and then the polycrystalline silicon layer is patterned to form a gale electrode 204 of a p-channel TFT which constitutes a load transistor. Gate electrode 204 is formed to be connected to gate electrode 202 of a driver transistor in a part.
Then, as illustrated in FIG. 21B, an oxide film, for example, which constitutes a gate insulating film 212 is formed on the whole surface by a low pressure CVD process. Gate insulating film 212 is patterned as needed, and then a third layer of a polycrystalline silicon layer is formed by a low pressure CVD process, for example. The polycrystalline silicon layer is patterned to form a polycrystalline silicon layer 206 to be source, channel and drain regions of a TFT. A region of polycrystalline silicon layer 206 corresponding to the drain region of the TFT is connected to gate electrode 204 of another TFT.
As illustrated in FIG. 21C, a photoresist film 217 is formed only on a part of polycrystalline silicon layer 206 corresponding to the channel region. BF.sub.2, for example, is introduced into polycrystalline silicon layer 206 by ion implantation using photoresist film 217 as a mask. Then, photoresist film 217 is removed, and heat treatment is carried out so that boron is diffused in polycrystalline silicon layer 206. A source region 206a and a drain region 206b are formed by this.
A SRAM is characterized by smaller power consumption as compared with that of a DRAM. Therefore, a SRAM is used in portable type computer or word processor, an IC card, and the like, apart from general electronic equipment. These portable products are used with batteries, so that the power consumption of a SRAM must be made lower.
In the case of a conventional SRAM using a high resistance load type memory cell, it is necessary to increase the resistance value of a load in order to reduce the power consumption. However, if the resistance value is increased, there is the disadvantage that the stability of a memory cell is lowered, and the stored contents are changed. On the other hand, in the case of a SRAM using a memory cell adopting a TFT as a load transistor, there is the advantage that both of low power consumption and stability of a memory cell can be achieved. Therefore, a SRAM with a high performance is provided by providing a TFT with a high performance. In order to provide a TFT with a high performance, it is necessary to provide a TFT having characteristics as described in the following.
As illustrated in FIG. 19, source region 206a of the TFT also serves as power supply interconnection line Vcc. Therefore, it is necessary to suitably lower the electrical conduction resistance of the source region. In order to achieve this, it is necessary to raise the impurity concentration of the source/drain regions of the TFT. However, if the impurity concentration of the source/drain regions is made higher, the electric field at the junction of the channel region and the drain region becomes stronger, more electrons tend to flow from the drain region to the channel region, so that the leakage current is increased, and this is a problem. If the leakage current in OFF state of a TFT constituting a load transistor is increased, current for holding the state of storing data, i.e. power consumption during waiting is increased. In other words, the drain current in the case where a TFT constituting a load transistor is in OFF state is increased. On the other hand, if the impurity concentration of the source/drain region is lowered for reducing the leakage current, there is a problem of higher electrical conducting resistance of the interconnection region constituting the power supply interconnection line or the like, which deteriorates the operational performance of the SRAM. As described above, when a p-channel TFT is applied to a CMOS-type SRAM memory cell, it is necessary to make the leakage current in the nonoperating state of the TFT as small as possible for making power consumption during waiting as small as possible.
Referring to FIG. 16A, when memory cell node N1 has a potential at "High" level, and memory cell node N2 has a potential at "Low" level, driver transistor Q3 is in OFF state, and driver transistor Q4 is in ON state. At this time, a potential at "Low" level is applied to the gate electrode of load transistor Q5 implemented with a p-channel TFT, so that load transistor Q5 is in ON state. A potential at "High" level is applied to the gate electrode of load transistor Q6 implemented with a p-channel TFT, so that load transistor Q6 is in OFF state. Memory cell node N1 is charged from power supply Vcc through load transistor Q5 in ON state, so that its potential is kept at "High" level. Leakage current is supplied from power supply Vcc through load transistor Q6 in OFF state to memory cell node N2, so that its potential is kept at "Low" level. Thus, data can be held.
In this case, driver transistor Q3 in OFF state is implemented with a bulk-type n-channel MOS transistor formed on a semiconductor substrate, so that leakage current is generated in driver transistor Q3 because of generation of a noise charge caused by alpha rays or the like from the outside. Therefore, the potential of memory cell node N1 is a little lower than "High" level. In order to counteract the effects of generation of the noise charge, it is necessary to increase the current supplied for keeping the potential of memory cell node N1 at "High" level, i.e. the drain current of load transistor Q5 in 0N state. Accordingly, when a load transistor is implemented with a p-channel TFT, it is necessary to form the TFT so that the drain current during operation is as large as possible for stabilizing the data holding characteristic.
Furthermore, as illustrated in FIG. 21C, the positional relation between gate electrode 204 of a p-channel TFT and source/drain regions 206a, 206b is determined by the position of photoresist film 217 formed by a photolithography technique. Therefore, there is a problem that source/drain regions 206a, 206b cannot be formed in a self-align manner with gate electrode 204.